Synopsys has announced that its design process tools and IP are ready for the 2nm manufacturing process at Samsung wafer foundries. Samsung recently announced that it will mass produce 2nm process semiconductor chips in 2025 and stated that the process will be further improved in 2027. Synopsys' EDA design tool has passed Samsung's 2nm GAA process certification.
According to the official introduction, Synopsys' EDA kit can improve the simulation design migration, PPA (area efficiency, performance, and energy efficiency), and productivity of Samsung wafer foundry 2nm GAA process nodes. Synopsys utilizes artificial intelligence (AI) for collaborative optimization to help Samsung improve the area efficiency, performance, and energy efficiency of the 2nm process.
Synopsys' DSO.ai and ASO.ai tools have been successfully migrated from FinFET to GAA architecture, which means that customers can smoothly migrate their existing FinFET chip designs to the new 2nm GAA process.
Chip companies can use Synopsys tools to develop new chip design technologies, including backside power supply wiring, local layout effect perception methods, and nanosheet unit design, thereby improving the efficiency and performance of SF2 processes. Samsung stated that the SF2Z process node can further improve performance, power consumption, and density (by 20%).
Synopsys also revealed that its UCIE IP has been used in the production of chips at Samsung SF2 and SF4x process nodes. In addition, the same DTCO solution will also be used to optimize Samsung's 1.4nm process node (SF1.4).
