Description: CADENCE LIRARIES/INTRFC MAINT
Description: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Description: EXEMPLAR SYNTHESIS LIBS/INTRFC
Description: SYNOPSYS LIBRARIES/INTRFC MAINT
Description: INTEGRAPH SCHEM SYNTH/SIM MAINT
Description: SOFTWARE DESIGN PROCHIP
Description: MAINT EXEMPLAR SYNTHESIS
Description: PRO CHIP SOFTWARE LICENSE
Description: SYNOPSYS LIBRARIES/INTRFC MAINT
Description: MENTOR V8 LIBRARIES/INTRFC MAINT
Description: CADENCE VERILOG LIB/INTRFC MAINT
Description: EXEMPLAR SYNTHESIS LIBS/INTRFC
Description: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
Description: ATMEL SYNARIO VERILOG SIM OPTION
Description: ATMEL SYNARIO VHDL SYNTHESIS OPT
Description: ATMEL SYNARIO VHDL SYNTHESIS OPT
Description: ATMEL SYNARIO BASIC PACKAGE
Description: MENTOR V8 LIBRARIES/INTERFACE
Description: UNIV AT6000 PHYSICAL DESIGN SYS
Description: FPGA DESIGN SYSTEM W/VIEWDRAW